A randomly accessible, single-port memory device is a memory device that allows access to one memory address per clock cycle. In contrast, a dual-port memory device allows two memory addresses to be simultaneously accessed (e.g., written to and/or read from) during a single clock cycle. For example, with a dual-port memory device having two ports (e.g., port A and port B), during a single clock cycle, data may be read from address A on port A while data is being written to address B on port B. Consequently, dual-port memory devices are often utilized in multiprocessor systems having two (or more) processors that require simultaneous access to data stored in a single memory array.
There are several techniques for implementing a dual-port random access memory device. One type of conventional dual-port memory device is based on an array of dual-port memory cells. That is, the individual memory cells are designed to allow simultaneous read/write access during a single clock cycle. FIG. 1 illustrates an example of a conventional true dual-port memory cell. As illustrated in FIG. 1, the dual-port memory cell 10 has two sets of complimentary bit-lines 12, 14, 16 and 18—one set for each port (e.g., port A and port B). In addition, each bit line is connected to a row-select transistor, or “pass” gate (e.g., transistors T5, T6, T7 and T8). Each row-select transistor is connected to a word-line 20 and 22 that is asserted during a read or write operation to facilitate the reading or writing of the memory cell. Compared to a single-port memory cell, a true dual-port memory cell 10 has twice the number of bit-lines, word-lines, and row-select transistors per individual memory cell. Consequently, compared to an array of single-port memory cells, an array of true dual-port memory cells occupies a significantly greater area of silicon per memory device and is therefore generally more costly to implement than an array based on single port memory cells.
As a result, a variety of dual-port memory devices that utilize single-port memory cells have been designed. One technique for implementing a dual-port memory device with an array of single-port memory cells is to partition the single-port memory array so that one address within each partition can be accessed simultaneously during a single clock cycle. Collision detection and correction logic is utilized to detect when both addresses are in the same partition. Generally, the greater the number of partitions, the less chance that both ports will attempt to access an address on the same partition during the same clock cycle. However, as more and more partitions are added, the complexity and size of the access control logic (e.g., the read/write logic) and collision detection logic increases. Furthermore, restricting access to addresses in different partitions during a single clock cycle is an undesirable limitation.
Another technique for emulating a dual-port memory device with an array of single-port memory cells is by utilizing a second clock signal to operate the memory device at twice the speed (e.g., frequency) of the system clock. For example, a second clock generating circuit, external to the memory device, may be used to generate a second clock signal, which operates at a frequency twice that of the system clock, or core clock. Accordingly, the processor and all other portions of the circuit are clocked at the frequency of the system or core clock, while the memory device is configured to operate at the frequency of the second clock (twice the frequency of the core clock).
FIG. 2 illustrates an example of a circuit 24 having a dual-port memory device 26 with an array of single-port memory cells 28, based on a dual clock signal design. For example, in the circuit 24 illustrated in FIG. 2, the dual-port memory device 26 operates in a clock domain 30 that is different from the core clock domain 32. Accordingly, the circuit 24 includes clock balancing and synchronization logic 34. The clock balancing and synchronization logic 34 receives a core clock signal, which cycles high and low at a particular frequency (e.g., 500 Megahertz), and generates a memory clock signal that cycles high and low at twice the frequency of the core clock signal. Accordingly, the multiplexing read and write logic 36 routes address and data signals to the single-port memory device 26 at a frequency (e.g., 500 Megahertz) that is half of that at which the single-port memory device operates (e.g., 1 Gigahertz). Consequently, the single-port memory device can simulate a dual-port memory device by operating based on a clock signal that has a frequency that is two times greater than the core clock signal.
There are several problems associated with this last approach. In particular, utilizing a second clock signal to operate the single-port memory device at twice the speed of the core clock presents a variety of clock timing, clock-domain, and performance degradation issues. First, as core clock frequencies continue to increase, so too does the level of difficulty in designing logic to synchronize a second clock with the core clock. For example, a system developer may have to spend a significant amount of development time designing and testing the clocking logic and synchronization logic that serves as the interface between the memory device and the system. In addition, the additional clock and synchronization logic occupy valuable space on the silicon of the chip, potentially increasing the size and cost of the system. Finally, the extra logic may introduce performance degradation into the system due to one or more delays during which read and write operations are allowed proper set-up and hold times for data. Consequently, there exists a need for an improved dual-port memory design.